Systems, methods, and apparatuses for implementing die recovery in two-level memory (2lm) stacked die subsystems

ABSTRACT

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems. For instance, there is disclosed in accordance with one embodiment a stacked semiconductor package having therein: a processor functional silicon die at a first layer of the stacked semiconductor package; one or more memory dies forming a corresponding one or more memory layers of the stacked semiconductor package; a plurality of Through Silicon Vias (TSVs) formed through the one or more memory dies, wherein each of the plurality of TSVs traverse through the one or more memory layers to the processor functional silicon die at the first layer of the stacked semiconductor package; a plurality of physical memory interfaces electrically interfacing the one or more memory dies to the processor functional silicon die at the first layer through the memory layers via the plurality of TSVs; a redundant physical memory interface formed by a redundant TSV traversing through the memory layers to the processor functional silicon die at the first layer through which to reroute a memory signal path from a defective physical memory interface at a defective TSV to a functional signal path traversing the redundant TSV. Other related embodiments are disclosed.

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TECHNICAL FIELD

The subject matter described herein relates generally to the field ofsemiconductor and electronics manufacturing, and more particularly, tosystems, methods, and apparatuses for systems, methods, and apparatusesfor implementing die recovery in Two-Level Memory (2LM) stacked diesubsystems.

BACKGROUND

The subject matter discussed in the background section should not beassumed to be prior art merely as a result of its mention in thebackground section. Similarly, a problem mentioned in the backgroundsection or associated with the subject matter of the background sectionshould not be assumed to have been previously recognized in the priorart. The subject matter in the background section merely representsdifferent approaches, which in and of themselves may also correspond toembodiments of the claimed subject matter.

The modern consumer electronics market frequently demands complexfunctions requiring very intricate circuitry. Scaling to smaller andsmaller fundamental building blocks, (e.g. transistors), has enabled theincorporation of even more intricate circuitry on a single die with eachprogressive generation. Semiconductor packages are used for protectingan integrated circuit (IC) chip or die, and also to provide the die withan electrical interface to external circuitry. With the increasingdemand for smaller electronic devices, semiconductor packages aredesigned to be even more compact and must support increased circuitdensity.

One solution to such a problem is to stack the functional silicondevices into 3D (three dimensional) semiconductor packages formed frommultiple functional silicon dies including one or more memories and oneor more logic dies.

The more densely packed the functional elements become within any givensemiconductor package, the better the performance will be for thatsemiconductor package as there can be more “stuff” within the samephysical space capable of performing functional aspects of thefunctional semiconductor silicon dies and devices of the semiconductorpackage and the shorter the information must travel, thus resulting infaster processing.

Reducing the total space occupied by the same number of functionalsilicon dies helps to address this problem by stacking the functionalsilicon dies into a package to realize such physical space reductions.

But such a solution introduces additional complexity and bringsadditional problems which must now be addressed.

The present state of the art may therefore benefit from the means forimplementing die recovery in Two-Level Memory (2LM) stacked diesubsystems as described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are illustrated by way of example, and not by way oflimitation, and will be more fully understood with reference to thefollowing detailed description when considered in connection with thefigures in which:

FIG. 1A depicts an exemplary stacked semiconductor device in accordancewith which embodiments may operate;

FIG. 1B depicts an exemplary stacked semiconductor device in accordancewith which embodiments may operate;

FIG. 2 depicts an exemplary stacked semiconductor device having a faultyor defective TSV identified therein along with a recovery procedure;

FIG. 3 depicts another exemplary stacked semiconductor device having afaulty or defective TSV identified therein along with a recoveryprocedure;

FIG. 4 depicts another exemplary stacked semiconductor device having afaulty or defective TSV in accordance with described embodiments;

FIG. 5 depicts a TSV pillar re-routing map for two channels of theDDR/DRAM memory address lines, CA[10:0] in accordance with describedembodiments;

FIG. 6 depicts a table which may be used for shifting the addresssignals for any possible failed lane in accordance with describedembodiments;

FIG. 7 depicts an exemplary process flow implementing a detour fusedownloading and distribution scheme in accordance with describedembodiments;

FIG. 8 is a schematic of a computer system in accordance with describedembodiments;

FIG. 9 illustrates an interposer that includes one or more describedembodiments;

FIG. 10 illustrates a computing device in accordance with oneimplementation of the invention; and

FIG. 11 is a flow diagram illustrating a method for implementing dierecovery in Two-Level Memory (2LM) stacked die subsystems in accordancewith described embodiments.

DETAILED DESCRIPTION

Described herein are systems, methods, and apparatuses for implementingdie recovery in Two-Level Memory (2LM) stacked die subsystems. Forinstance, there is disclosed in accordance with one embodiment a stackedsemiconductor package having therein: a processor functional silicon dieat a first layer of the stacked semiconductor package; one or morememory dies forming a corresponding one or more memory layers of thestacked semiconductor package; a plurality of Through Silicon Vias(TSVs) formed through the one or more memory dies, wherein each of theplurality of TSVs traverse through the one or more memory layers to theprocessor functional silicon die at the first layer of the stackedsemiconductor package; a plurality of physical memory interfaceselectrically interfacing the one or more memory dies to the processorfunctional silicon die at the first layer through the memory layers viathe plurality of TSVs; a redundant physical memory interface formed by aredundant TSV traversing through the memory layers to the processorfunctional silicon die at the first layer through which to reroute amemory signal path from a defective physical memory interface at adefective TSV to a functional signal path traversing the redundant TSV.

In the following description, numerous specific details are set forthsuch as examples of specific systems, languages, components, etc., inorder to provide a thorough understanding of the various embodiments. Itwill be apparent, however, to one skilled in the art that these specificdetails need not be employed to practice the embodiments disclosedherein. In other instances, well known materials or methods have notbeen described in detail in order to avoid unnecessarily obscuring thedisclosed embodiments.

In addition to various hardware components depicted in the figures anddescribed herein, embodiments further include various operations whichare described below. The operations described in accordance with suchembodiments may be performed by hardware components or may be embodiedin machine-executable instructions, which may be used to cause ageneral-purpose or special-purpose processor programmed with theinstructions to perform the operations. Alternatively, the operationsmay be performed by a combination of hardware and software.

Any of the disclosed embodiments may be used alone or together with oneanother in any combination. Although various embodiments may have beenpartially motivated by deficiencies with conventional techniques andapproaches, some of which are described or alluded to within thespecification, the embodiments need not necessarily address or solve anyof these deficiencies, but rather, may address only some of thedeficiencies, address none of the deficiencies, or be directed towarddifferent deficiencies and problems which are not directly discussed.

Implementations of embodiments of the invention may be formed or carriedout on a substrate, such as a semiconductor substrate. In oneimplementation, the semiconductor substrate may be a crystallinesubstrate formed using a bulk silicon or a silicon-on-insulatorsubstructure. In other implementations, the semiconductor substrate maybe formed using alternate materials, which may or may not be combinedwith silicon, that include but are not limited to germanium, indiumantimonide, lead telluride, indium arsenide, indium phosphide, galliumarsenide, indium gallium arsenide, gallium antimonide, or othercombinations of group III-V or group IV materials. Although a fewexamples of materials from which the substrate may be formed aredescribed here, any material that may serve as a foundation upon which asemiconductor device may be built falls within the spirit and scope ofthe present invention.

A plurality of transistors, such as metal-oxide-semiconductorfield-effect transistors (MOSFET or simply MOS transistors), may befabricated on the substrate. In various implementations of theinvention, the MOS transistors may be planar transistors, nonplanartransistors, or a combination of both. Nonplanar transistors includeFinFET transistors such as double-gate transistors and tri-gatetransistors, and wrap-around or all-around gate transistors such asnanoribbon and nanowire transistors. Although the implementationsdescribed herein may illustrate only planar transistors, it should benoted that the invention may also be carried out using nonplanartransistors.

Each MOS transistor includes a gate stack formed of at least two layers,a gate dielectric layer and a gate electrode layer. The gate dielectriclayer may include one layer or a stack of layers. The one or more layersmay include silicon oxide, silicon dioxide (SiO₂) and/or a high-kdielectric material. The high-k dielectric material may include elementssuch as hafnium, silicon, oxygen, titanium, tantalum, lanthanum,aluminum, zirconium, barium, strontium, yttrium, lead, scandium,niobium, and zinc. Examples of high-k materials that may be used in thegate dielectric layer include, but are not limited to, hafnium oxide,hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide,zirconium oxide, zirconium silicon oxide, tantalum oxide, titaniumoxide, barium strontium titanium oxide, barium titanium oxide, strontiumtitanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalumoxide, and lead zinc niobate. In some embodiments, an annealing processmay be carried out on the gate dielectric layer to improve its qualitywhen a high-k material is used.

The gate electrode layer is formed on the gate dielectric layer and mayconsist of at least one P-type workfunction metal or N-type workfunctionmetal, depending on whether the transistor is to be a PMOS or an NMOStransistor. In some implementations, the gate electrode layer mayconsist of a stack of two or more metal layers, where one or more metallayers are workfunction metal layers and at least one metal layer is afill metal layer.

For a PMOS transistor, metals that may be used for the gate electrodeinclude, but are not limited to, ruthenium, palladium, platinum, cobalt,nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-typemetal layer will enable the formation of a PMOS gate electrode with aworkfunction that is between about 4.9 eV and about 5.2 eV. For an NMOStransistor, metals that may be used for the gate electrode include, butare not limited to, hafnium, zirconium, titanium, tantalum, aluminum,alloys of these metals, and carbides of these metals such as hafniumcarbide, zirconium carbide, titanium carbide, tantalum carbide, andaluminum carbide. An N-type metal layer will enable the formation of anNMOS gate electrode with a workfunction that is between about 3.9 eV andabout 4.2 eV.

In some implementations, the gate electrode may consist of a “U”-shapedstructure that includes a bottom portion substantially parallel to thesurface of the substrate and two sidewall portions that aresubstantially perpendicular to the top surface of the substrate. Inanother implementation, at least one of the metal layers that form thegate electrode may simply be a planar layer that is substantiallyparallel to the top surface of the substrate and does not includesidewall portions substantially perpendicular to the top surface of thesubstrate. In further implementations of the invention, the gateelectrode may consist of a combination of U-shaped structures andplanar, non-U-shaped structures. For example, the gate electrode mayconsist of one or more U-shaped metal layers formed atop one or moreplanar, non-U-shaped layers.

In some implementations of the invention, a pair of sidewall spacers maybe formed on opposing sides of the gate stack that bracket the gatestack. The sidewall spacers may be formed from a material such assilicon nitride, silicon oxide, silicon carbide, silicon nitride dopedwith carbon, and silicon oxynitride. Processes for forming sidewallspacers are well known in the art and generally include deposition andetching process steps. In an alternate implementation, a plurality ofspacer pairs may be used, for instance, two pairs, three pairs, or fourpairs of sidewall spacers may be formed on opposing sides of the gatestack.

As is well known in the art, source and drain regions are formed withinthe substrate adjacent to the gate stack of each MOS transistor. Thesource and drain regions are generally formed using either animplantation/diffusion process or an etching/deposition process. In theformer process, dopants such as boron, aluminum, antimony, phosphorous,or arsenic may be ion-implanted into the substrate to form the sourceand drain regions. An annealing process that activates the dopants andcauses them to diffuse further into the substrate typically follows theion implantation process. In the latter process, the substrate may firstbe etched to form recesses at the locations of the source and drainregions. An epitaxial deposition process may then be carried out to fillthe recesses with material that is used to fabricate the source anddrain regions. In some implementations, the source and drain regions maybe fabricated using a silicon alloy such as silicon germanium or siliconcarbide. In some implementations the epitaxially deposited silicon alloymay be doped in situ with dopants such as boron, arsenic, orphosphorous. In further embodiments, the source and drain regions may beformed using one or more alternate semiconductor materials such asgermanium or a group III-V material or alloy. And in furtherembodiments, one or more layers of metal and/or metal alloys may be usedto form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOStransistors. The ILD layers may be formed using dielectric materialsknown for their applicability in integrated circuit structures, such aslow-k dielectric materials. Examples of dielectric materials that may beused include, but are not limited to, silicon dioxide (SiO₂), carbondoped oxide (CDO), silicon nitride, organic polymers such asperfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass(FSG), and organosilicates such as silsesquioxane, siloxane, ororganosilicate glass. The ILD layers may include pores or air gaps tofurther reduce their dielectric constant.

FIG. 1A depicts an exemplary stacked semiconductor device 101 inaccordance with which embodiments may operate.

In particular, the depicted semiconductor device 101 embodies aTwo-Level Memory (2LM) stacked die subsystem having both a System On aChip (SOC) die 105 at a bottom layer also called “logic die” or afunctional silicon die or a functional semiconductor device and then amemory die (e.g., memory die-1) 110 at a top layer. There is furtherdepicted a substrate 150 which is interfaced with the SOC-die 105 andthe memory die 110 via the Ball Grid Array (BGA) 140 as shown.Electrical interconnects of the top memory die 110 are electricallyinterfaced to the substrate 150 first through the Through Silicon Vias(TSVs) 135 as shown and then through the BGA and into the substrate 150.

Additionally depicted are the solder balls 145 to provide electricalconnectivity between the substrate and another board, such as a mainboard, a Printed Circuit Board (PCB) motherboard, etc.

The stacked semiconductor device 101 depicted here provides one or morethree dimensional (3D) stacked memory modules (e.g., memory die-1 atelement 110) which are tightly integrated into the microprocessors, suchas SOC-die 105.

Such technology meets the low power consumption and high bandwidthrequirements now demanded by the computing industry and consumerelectronics marketplace.

Consequently, it is of critical importance that such memory dies (e.g.,memory die-1) operate reliably as the integrated components cannot beswapped out after manufacture. State differently, failure of a singleintegrated component necessitates replacement of the entire stackedsemiconductor device 101 at great expense.

According to one embodiment, a first memory layer is formed from a DRAMsemiconductor die. According to a particular embodiment, the DRAM isglued or affixed to the SOC die or another logic die. According toanother a second level memory die is formed from a phase change memory.Phase-change memory or SXP memory (also known as PCM, PCME, PRAM, PCRAM,Ovonic Unified Memory, Chalcogenide RAM and C-RAM) is a type ofnon-volatile random-access memory. By keeping the memory physicallycloser to the CPU die, logic die, or SOC die as is depicted here,critical applications are able to run faster.

According to certain embodiments, the memory dies form near memory forthe SOC die which may be utilized as caching memory due to its closeproximity with the SOC die.

FIG. 1B depicts an exemplary stacked semiconductor device 102 inaccordance with which embodiments may operate.

In particular, there is depicted a System On a Chip (SOC) attached to astack for the memory dies using TSVs 135 in which the TSVs provideconnectivity from the uppermost memory die-4 at element 125 down throughopenings formed through each of the memory dies 3, 2, and 1, at elements120, 115, and 110 respectively, and ultimately through the SOC-die 105to the BGA 140 layer and into the substrate 150 which as before may beconnected with another main board or PCB motherboard, etc., using thesolder balls 145.

As shown, a memory module stack 130 is formed from the memory dies 1, 2,3, and 4 (elements 110, 115, 120, and 125) providing memory to theSOC-die 105 within a single 3D stacked semiconductor package 102.

As depicted here, the stacked memory dies 1, 2, 3, and 4 (elements 110,115, 120, and 125) are connected to one to another and also to the CPUembodied within the SOC-die 105 through the TSV 135 interconnects. TheTSVs are leveraged in such a design to enable the vertical stacking ofsuch memory chips. The 3D stacked semiconductor approach is especiallybeneficial at wafer level packaging permitting “vias” to be opened(e.g., a trench or opening etched into the material) from the front sideof the wafer all the way through the wafer and then out the back of thewafer, forming, in essence, a hole through the functional semiconductordevice. The vias or TSVs formed through the functional silicon devicesmay vary in diameter from 1 μm (micron) to 10 μm with a depth typicallybeing 5 to 10 times the width.

The TSVs 135 provide a critical communications interface from the upperlevel functional dies, be they memory dies, SOC dies, logic dies, orotherwise, to the substrate below. Any stress to the TSVs 135 resultingfrom the assembly process, random defects or anomalies, or evensystematic defects in the manufacturing process which forms the TSVs 135at the per-functional silicon die level or at the assembled stackedsemiconductor device 102 level has the potential to render the entiremanufactured stacked semiconductor device 102 useless. It is alsofeasible that the TSV operates when formed and even when the dies areintegrated into the stacked semiconductor device 102 but then failshortly after, for instance, due to high electrical stress, due totemperature changes, and so forth. Through testing it is possible tocause such early life failures of the devices to occur duringmanufacturing and testing processes during which time the faulty TSVsmay also therefore be re-worked, thus preventing scrap loss and alsopreventing such failure modes from reaching consumers.

Conventionally, defective stacked semiconductor device 102 necessitatedscrapping the entire stacked semiconductor device 102 as it could not bere-worked and having even a single TSV 135 amongst the many utilizedresulted in reduced functionality or non-functionality for the entirestacked semiconductor device 102.

More problematically, certain stacked semiconductor device 102 embodynot just functional silicon devices such as SOC-dies 105 or logic diesmanufactured by the producer of the stacked semiconductor device 102 butadditionally embody memory dies (110, 115, 120, 125) purchased fromexternal third party companies, meaning that purchase product which wasto be integrated into a finished product was also scrapped, resulting ina substantial financial loss to the manufacturer of the stackedsemiconductor device 102.

Moreover, manufacturing of the TSVs 135 is an inherently complex processand depending on the precise methodologies, the process of forming theTSVs 135 results in anywhere from a 10-12% yield loss which translatesin turn to upwards of 200 million dollars in financial lossesattributable to the manufacturer of such products due to TSV 135 defectsand scrap at the per-device and stacked semiconductor device 102 level,with the scrap of any finished stacked semiconductor device 102 beingmuch more costly.

It is therefore in accordance with described embodiments that a TSV 135repair process is utilized to permit the recovery of such stackedsemiconductor devices 102 even in the presence of a faulty or defectiveTSV 135 embedded within the stacked semiconductor device 102.Statistical analysis reveals that such a repair process is shouldrecover approximately 99.95% of previously unworkable and thereforescrapped product, thus providing a cost savings which far outweighs theadditional cost necessary to implement the described methodologies.

FIG. 2 depicts an exemplary stacked semiconductor device 201 having afaulty or defective TSV 240 identified therein along with a recoveryprocedure.

In particular, there is depicted an SOC and DRAM embodied within asingle package 203, thus forming the stacked semiconductor device 201.The top layer is formed by the DRAM 250 which is stacked upon the bottomSOC 251 layer. Multiple TSVs provide interconnectivity from the DRAM 250on top through the SOC 251 below.

Within the DRAM 250 it may be observed multiple TSVs including thedefective TSV 240 on the far right, a redundant TSV 235 on the far left.From left to right, there are TSV connections DA 264 to DA 261 (whichforms the redundant TSV 235), then D1 265 to D1 261, then Dn-1 266 toDn-1 262 and finally Dn 267 to Dn 263 (which is the identified defectiveTSV 240).

Although four such TSVs are depicted here for the purposes ofillustration, there may be and very likely will be many more TSVs forany given stacked semiconductor device 201.

Additionally depicted are the top traffic re-router logic 215 of theDRAM 250 and the bottom traffic re-router logic 220 of the SOC 251. Anon package secured connection 206 and clock serial data 207 areadditionally provided.

The FLASH ROM or fuse RAM 204 is shown flowing to data shifter 225, toregister 230, to data shifter 225, to the clock serial data 207 to theon package secured connection 206 and then around to the upper layer'sdata shifters 205 and registers 210. The registers 210 of the top layerand the registers 230 of the bottom layer are communicably interfacedwith the traffic re-router logics 215 and 220 respectively.

It is therefore in accordance with described embodiments that a varietyof algorithms and low cost hardware DFX infrastructure (DFX is “Designfor X” or “Design For Excellence” in the context of manufacturing).

According to a particular embodiment, having identified a defective TSV240 a “traffic detour string” is calculated to determine detour routeswhich permit the traffic from the upper layer DRAM 250 to be re-routedor detoured through one or more redundant TSVs 235.

For instance, on every cold-boot of the stacked semiconductor device thetraffic detour string is downloaded from a fuse bank or the registers230 on the SOC 251 side where a CPU resides. According to such anembodiment, a secure link is then established from the SOC 251 layer tothe DRAM 250 layer through the data shifters 225 and 205 as depicted theon package secured connection 206.

For instance, utilizing a built-in safe network from a CPU of the SOC251 the stacked DRAM 250 module the traffic-detour string is thenshifted into the DRAM 250 module. Once the traffic-detour string isreceived at the DRAM 250 the data shifters 205 of the DRAM 250 may thenprogram the registers 210 of the DRAM to enable the data shift or thedata detour based on the received and previously computed traffic detourstring.

According to a particular embodiment, the introduction and inclusion ofas few as 192 storage bits via the registers 210 and 230 it is thenpossible to recover the yields from previously scrapped stackedsemiconductor devices 201 having faulty or defective TSVs 240 by up to99.95%.

According to particular embodiments, third party DRAM vendors (e.g.,providing DRAM 250 module embedded with a stacked semiconductor device201 by the manufacturer of the CPU and SOC 251) incorporate the register210 storage bits via their own manufacturing processes, thus embodyingthe needed registers 210 and data shifter 205 logic within their devicesat very little cost and effort pursuant to provided technicalspecifications as provided by the manufacturer of the CPU, SOC 251, andresulting stacked semiconductor device 201.

Additionally, utilizing a 2-wire interconnect within the stackedsemiconductor device 201 the on package secured connection 206 isembodied within the stacked semiconductor device 201 capable to transferthe TSV detour string from the SOC 251 die fabricated and manufacturedby a first manufacturer to the DRAM 250 or other memory device, evenwhen manufactured by another third party manufacturer.

According to such embodiment, a 2-wire interface is provided within thestacked semiconductor device 201 thus permitting on package secureconnections from the SOC 251 to the DRAM 250. According to such anembodiment, a mirrored image of the TSV detour string from the SOC 251is transmitted to the third party manufacturer supplied DRAM 250 siliconmodule that is integrated the final stacked semiconductor device 201 endproduct.

No prior solutions for TSV repair are available to the marketplacepresently.

Because the dedicated two wires are embedded within the stackedsemiconductor device 201 to transfer the data from SOC 251 die to theDRAM 250 die, any signals transmitted thereupon simply cannot beintercepted by any hackers as there is no externally facing interface.Thus, it is not possible for hackers to derive any data flow transferredinto the DRAM or even derive whether the signal traverses its intendedTSV or a redundant TSV. Moreover, the re-routing capability isconfigurable on a per-unit basis for each stacked semiconductor device201 manufactured, thus permitted extensive flexibility within a HighVolume Manufacturing (HVM) environment. Such flexibility is needed asdefects and faults may arise as random anomalies thus necessitatingdifferent routing schemes for any particular device. Because everystacked semiconductor device 201 unit manufactured may be programmeddifferently, it is possible to fully recover any device having a singleTSV failure where just one redundant TSV is provided. Additionally, dueto the very low memory requirements (e.g., as few as 192 bits ofregister storage) the solution also represents a very low cost to thirdparty DRAM 250 vendors which provide additional dies to the manufacturerof the CPU and SOC 251 die who also integrates and manufactures thestacked semiconductor device 201.

According to a particular embodiment, implementing the TSV signalre-routing includes first identifying any defective micro pillarsassociated with the TSVs in any stacked semiconductor device 201manufactured, then computing a detour string through an algorithm thatre-routes DRAM address and data signals as described in additionaldetail below, and then storing the computed detour strings securelywithin a fuse bank which is not externally accessible. During a cold orwarm boot, the stacked semiconductor device 201 then downloads itsre-routing string and shifts the string from the SOC 251 die to one ormore upper memory DRAM 250 dies which each then securely store there-routing string within their fuse banks so as to implement the neededTSV path re-routing during operation.

FIG. 3 depicts another exemplary stacked semiconductor device 301 havinga faulty or defective TSV 240 identified therein along with a recoveryprocedure.

As depicted here, TSV pillar DQ2 is defective and a correspondingre-routing of the traffic is therefore shown with the traffic re-routingconstituting a shift by 1 in this specific example. In this scheme thesignal intended for TSV pillar DQ2 is routed through the DQ1 TSV pillarand the signals destined for TSV pillar DQ1 are re-routed to proceedthrough redundant pillar. Accordingly, in a non-defective mode, there-routing string for this particular example would be “0000” as therewould be no need to re-route when non-defective, however, because TSVpillar DQ2 is identified as defective, the re-routing string “1100” isutilized to cause the mux (multiplexer) to select the appropriate routesto detour traffic from the DRAM 310 side and the CPU or SOC 315 side.

In greater specificity, there is shown a stacked semiconductor device301 having, by way of example, the four TSV pillars, three of which areneeded for routing signals, and one of which is a redundant 305 TSVpillar through which signals or traffic between the two dies formed fromthe DRAM 310 and SOC 315 may be re-routed or detoured if necessary, suchas in the event of an identified defective TSV pillar within the stackedsemiconductor device 301.

As depicted here, the stacked semiconductor device 301 includes both aDRAM 310 module formed from the upper functional silicon die (here amemory die) and also a SOC 315 formed from the lower functional silicondie (here a CPU or logic die).

From the left to right, the left most TSV pillar forms a redundant 305TSV pillar meaning that if all of the TSV pillars are fully functional,the left most redundant 305 will not be needed and will therefore beembedded within the stacked semiconductor device 301 but simply will notbe used. However, there is depicted here a functional redundant 305 TSVpillar at the far left (TSV pillar NC), with another functional TSVpillar at the second from the left (TSV pillar DQ1), and then a faultyTSV pillar third from the left (TSV pillar DQ2), and finally anotherfunctional TSV pillar on the far right (TSV pillar DQ3).

Notably, each TSV pillar is connected with a mux and de-mux (decoder ordemultiplexer), permitting both S and 1L signal routes at each potentialTSV path, though only one is used for any TSV pillar, whether functionalor not. Rather than a straight fixed path, embodiments as describedherein permit any signal destined to traverse a specified TSV pillar toeither traverse the intended TSV pillar or to be re-routed or detouredthrough another TSV pillar. In such a way, where a defective TSV pillaris identified as is the case with TSV pillar DQ2, the signal may bere-routed or detoured through the neighboring TSV pillar.

As shown here, the rightmost signal traverses its specified and intendedTSV pillar, going from DQ3 through signal path S down through TSV pillarDQ3 and received at signal path S. This is normal and intended behavior.

However, TSV pillar DQ2 is identified as a defective TSV pillar, and thesignal path simply cannot be routed through the TSV pillar. Any signalrouted from DQ2 at the DRAM 310 side through signal path S to signalpath S of DQ2 at the SOC 315 side will fail.

Consequently, the signal path is re-routed instead to the neighboringTSV pillar, thus causing the signal intended for DQ2 to travel throughDQ1 instead. Therefore, the signal to travel through DQ2 is re-routed ordetoured to travel instead through signal path 1L of DQ1, theneighboring TSV pillar at the DRAM 310 side and through TSV pillar DQ1to signal path 1L of TSV pillar DQ1 at the SOC 315 side.

However, TSV pillar DQ1 can only carry a single signal and therefore,because its signal path has been consumed by its neighbor, it cannotcarry its own intended signal. Therefore, the data shifter as programmedvia the registers (refer to FIG. 2) re-routes the signal destined forDQ1 to its neighbor, thus causing the signal intended for DQ1 tore-route through signal path 1L of TSV pillar NC at DRAM 310 through TSVpillar NC (e.g., the redundant TSV pillar) down to signal path 1L at TSVpillar NC (e.g., the redundant TSV pillar) at the SOC 315 side.

Because any signal may be sent down either one of the two availablepaths using the provided muxes (multiplexers) it is therefore possibleto logically re-route the path taken by any signal through the availableTSVs, including detouring or re-routing the signals as necessary toavoid a defective TSV and instead route through a functional neighboringTSV. By then shifting each signal path to its neighbor the faulty TSVmay be avoided completely. The continuous shifting will eventually reachan edge or a last available TSV which is then routed to a neighboringredundant TSV whose function is not needed when all TSVs are functionalbut whose functionality may be leveraged for a repair and re-routingprocedure where a faulty TSV is identified.

The calculated routing string calculated is burnt into a fuse bank sothat it may be subsequently read out on any cold or warm boot procedure,after which that routing string is then propagated through the layers(e.g., the multiple semiconductor dies of the stack) such that everylayer is instructed how to route signals through the available TSVs,whether through a default route (e.g., a 0 in the string) or anon-default route (e.g., a 1 in the string).

Having determined the value of the routing string to fix any particularsemiconductor stack and having propagated the string, the data shiftersthen route the signals as appropriately by muxing any given signal toeither a default or non-default path, as necessary, so as to permit thesignal to traverse through the TSV pillars to its intended destination,notwithstanding the presence of a faulty TSV pillar.

According to described embodiments, determining whether a faulty TSV ispresent in the stacked semiconductor device, calculating the re-routingstring, and burning the re-routing string permanently into the fuse bankoccurs only once at the time of manufacture of that stackedsemiconductor device. Conversely, downloading the re-routing string,propagating it to the other layers of the stacked semiconductor deviceand performing the data/signal shifting via the available muxes at eachTSV pillar occurs at every cold boot and potentially at every warm boot.

According to one embodiment, the fuse bank comprises a plurality offuses which are burnt in on the CPU or SOC die side at the time ofmanufacture of the stacked semiconductor device and cannot be modifiedsubsequently. Consequently, the stacked semiconductor device willoperate in accordance with the determined re-routing procedure and thecalculated re-routing string permanently from then forward since theburnt fuses cannot be modified.

Therefore, according to a particular embodiment, processing at the timeof manufacture includes first, determining that a faulty TSV is presentwithin the stacked semiconductor package and then computing thenecessary re-routing string to fix or re-route signals around the faultyTSV, and then burning that re-routing string into the fuse bank (andoptionally testing to verify the re-routing string solves the problem)after which the configuration of that stacked semiconductor device ispermanent and cannot be modified. Therefore, subsequent resets of thestacked semiconductor device, even a cold reboot, will then cause thedevice to download or read the re-routing string from the registers ofthe fuse bank and then shift that string through the stackedsemiconductor device's various layers, causing the stacked semiconductordevice to shift its signals according to the re-routing string.

FIG. 4 depicts another exemplary stacked semiconductor device 401 havinga faulty or defective TSV 415 in accordance with described embodiments.Here, a faulty or defective TSV 415 is identified by an external testerwhich shifts vectors into the SOC and reads the capture data from theDRAM chains as depicted.

For instance, according to a particular embodiment, each of the capturedbits taken from the DRAM chain data are compared with expected datawhich was input by the external tester 425 at the SOC side so as toidentify which, if any, of the TSVs are associated with a fault and thusrequires repair via the data shift and re-routing procedure.

As can be seen here, there is an external tester 425 which is not partof the stacked semiconductor device 401 formed from the SOC and DRAMpackage 440 which includes at least a DRAM side 445 and an SOC side 450.

The external tester 425 is depicted as inputting shift data into the SOC435 which is then fed or transmitted through the connecting TSV pillars455 interfacing the respective DRAM and SOC sides 445 and 450. The datais then picked up and captured into the DRAM at element 430 as shownthrough the respective TSV pillars (from left to right) DQO at element405, DQ1 at element 410, DQ2 at element 415, and DQ3 at element 420.Ultimately the DRAM chain is data shifted out to the tester where thecaptured data from the DRAM side 445 may be compared with the shift data435 input into the SOC side 450, to determine whether or not the currentrouting configuration is faulty or non-faulty. For instance, if therouting is the default (e.g., routing string 0000 for a four pillarconfiguration) such that all data paths traverse their originallyintended TSV pillars, and the data compare at the tester 425 isacceptable, then it is not necessary to perform a re-routing procedure.However, if the default was previously identified as being faulty and are-routing procedure thus instituted, then the above procedure canidentify whether the re-routing is successful by inputting the shiftdata 435 at the SOC side 450 to traverse through the TSV pillars to theDRAM side 430 where the DRAM chain data is captured and shifted to thetester 425 for comparison as was done with the default configuration.

If the re-routing is also faulty after a data compare, then the correctrouting has not yet been attained and a new routing scheme can beprogrammed and tested.

According to a particular embodiment, the external tester 425communicates into the stacked semiconductor device 401 utilizing aninbuilt testing network (bus) of the stacked semiconductor device 401over which the tester 425 sends/shifts 435 a series of data bits intothe SOC chain at the SOC side 450. Next, a control signals from thetester to the DRAM stack captures previously sent data into the DRAMchain. The captured data is then shifted out of the DRAM chain andcollected by the tester 425 where it is compared against input valueswhere they are to be the same or against golden values where an expectedmodification of the values is expected and desirable. In such a way, itis possible to identify whether one of the TSV pillars utilized for thecurrent iteration is faulty because if any of the TSV values are faultythen the external tester 425 will not end up with the correct data, butrather, will have unexpected data which will be revealed as a non-matchwhen the collected values are compared against the input or expectedvalues.

When a fault is identified by the tester 425, a detour (rerouting)pattern is computed to produce a string causing the data shifters of thestacked semiconductor device 401 to bypass a faulty TSV micro-pillarassociated.

FIG. 5 depicts a TSV pillar re-routing map 501 for two channels of theDDR/DRAM memory address lines, CA[10:0] in accordance with describedembodiments.

In particular, at element 505 a TSV pin map—CA [10:0] is provided, whereDA8 on a first channel and DA9 on a second channel provide redundantpillars 504 (e.g., redundant TSVs). TSV Pillars CA0 through CA10 on thefirst and second channels Ch0 and Ch1 represent normal (e.g.,non-redundant or default) address pins 502 and 503 respectively for thefirst and second channels provided.

At elements 510 and 511 there is a TSV redundancy—Ch0 CA [10:0] Muxdirection (element 510) and a TSV redundancy Ch1 CA [10:0] Mux direction(element 511) for the first and second channels. Such a mapping may beutilized for all the data bits as well.

As shown, two redundant TSV pillars are provided, one for each of thetwo channels, DA8 and DA9. At elements 510 and 511, it may be observedthat a defect in Channel 0 necessitates detour or re-routing through themicro TSV pillar DA8 and a defect in channel 1 necessitates detour orre-routing through DA9. Additionally depicted here is the data shiftdirection in case of a faulty micro TSV pillar at each of the twochannels.

FIG. 6 depicts a table 601 which may be used for shifting the addresssignals for any possible failed lane in accordance with describedembodiments.

In particular, there is a Channel 0 CA[10:0] bus lane repair pin muxselection matrix providing the necessary detour encoding 699 beginningwith 0h, the mux selects 600 from the shifted-string chain, along withthe signal that appears on that lane, in the order of the signalsbeginning with CA9 , and then the various pins, starting with redundantTSV pillar DA8 at column 615, CA9 at column 620, CA10 at column 625, CA8at column 630, CA7 at column 635, CA6 at column 640, CA4 at column 645,CA5 at column 650, CA5 at column 655, CA2 at column 660, CA2 at column660, CA1 at column 665, and CA0 at column 670. Such a table may beutilized to compute the re-routing string for the data shifters (e.g.,225 and 205 at FIG. 2) for storage in the device registers (e.g., 210and 230 at FIG. 2). From the top mux select 600 beginning with 0h, thereis shown each of the mux selects for each lane, from 0h mux select 616,1h mux select 602, 2h mux select 614, 3h mux select 603, 4h mux select604, 4 h mux select 604, 5h mux select 605, 6h mux select 606, 7h muxselect 607, 8h mux select 608, 9 h mux select 609, Ah mux select 610, Bhmux select 611, and Ch to Fh mux select 612.

The more heavily hashed textured boxes indicate the pins which have beenmuxed and shifted to the left toward the DA8 pin at column 615. Theremaining lighter hashed textured boxes depict those pins which remainun-shifted, that is, they are pins which are not re-routed or detoured.

FIG. 7 depicts an exemplary process flow 701 implementing a detour fusedownloading and distribution 705 scheme in accordance with describedembodiments.

In particular, it may be observed within the provided detour fusedownloading and distribution 705 scheme that there is an SOC side of theTSV detour at block 740 and also a DRAM TSV repair 725 block havingtherein the detour registers. According to a particular embodiment,processing includes uploading the detour strings into the secured FuseRAM 710 as depicted by the SBR transmission 715 from the SOC side TSVrepair registers 720. Once the detour string is securely stored into afuse bank or the Secure fuse Bank Registers (SBR) then on any cold boot,the previously stored string is downloaded through the side band networkfrom the fuse RAM into the registers and into the SOC side logic. On awarm boot or warm (non-power loss or low-power mode transition) resetwhere the DRAM loses the value another transfer is triggered on the SOCside 740 to again download the re-routing string into the DRAM. Thedepicted FSM (Finite State machine) 745 takes the downloaded re-routingstring and transmits it as clock 730 and serial data 735 onto a two wirebus into the DRAM to carry out the DRAM TSV repair 725 (e.g., to enablethe re-routing at operation or run-time).

In accordance with one embodiment, propagating the re-routing stringcomprises propagating a binary string of 0's and 1's to the muxespresent at each TSV pillar causing the muxes to route signals down oneof two paths in accordance with the re-routing string's bit (e.g., 1 or0) at the position corresponding to that mux.

According to one embodiment, the re-routing string is propagated fromthe SOC die to one or more memory dies present within the stackedsemiconductor device via a secure onboard side band channel. Forinstance, consider that 50 bits are required to represent the fullre-routing string for a particular stacked semiconductor device. Ratherthan having 50 wires to transmit the entire string in parallel whichwould be very fast but extremely costly, two connecting wires areutilized for the secure onboard sideband channel through which the SOCdie will transmit the entirety of the re-routing string via a serialdata 735 transmission, one bit at a time, over 50 clock cycles for theexemplary 50-bit string.

FIG. 8 is a schematic of a computer system 800 in accordance withdescribed embodiments. The computer system 800 (also referred to as theelectronic system 800) as depicted can embody means for implementing dierecovery in Two-Level Memory (2LM) stacked die subsystems, according toany of the several disclosed embodiments and their equivalents as setforth in this disclosure. The computer system 800 may be a mobile devicesuch as a net-book computer. The computer system 800 may be a mobiledevice such as a wireless smart phone or tablet. The computer system 800may be a desktop computer. The computer system 800 may be a hand-heldreader. The computer system 800 may be a server system. The computersystem 800 may be a supercomputer or high-performance computing system.

In accordance with one embodiment, the electronic system 800 is acomputer system that includes a system bus 820 to electrically couplethe various components of the electronic system 800. The system bus 820is a single bus or any combination of busses according to variousembodiments. The electronic system 800 includes a voltage source 830that provides power to the integrated circuit 810. In some embodiments,the voltage source 830 supplies current to the integrated circuit 810through the system bus 820.

Such an integrated circuit 810 is electrically coupled to the system bus820 and includes any circuit, or combination of circuits according to anembodiment. In an embodiment, the integrated circuit 810 includes aprocessor 812 that can be of any type. As used herein, the processor 812may mean any type of circuit such as, but not limited to, amicroprocessor, a microcontroller, a graphics processor, a digitalsignal processor, or another processor. In an embodiment, the processor812 includes, or is coupled with, electrical devices having gradientencapsulant protection, as disclosed herein.

In accordance with one embodiment, SRAM embodiments are found in memorycaches of the processor. Other types of circuits that can be included inthe integrated circuit 810 are a custom circuit or anapplication-specific integrated circuit (ASIC), such as a communicationscircuit 814 for use in wireless devices such as cellular telephones,smart phones, pagers, portable computers, two-way radios, and similarelectronic systems, or a communications circuit for servers. In anembodiment, the integrated circuit 810 includes on-die memory 816 suchas static random-access memory (SRAM). In an embodiment, the integratedcircuit 810 includes embedded on-die memory 816 such as embedded dynamicrandom-access memory (eDRAM).

In accordance with one embodiment, the integrated circuit 810 iscomplemented with a subsequent integrated circuit 811. Usefulembodiments include a dual processor 813 and a dual communicationscircuit 815 and dual on-die memory 817 such as SRAM. In accordance withone embodiment, the dual integrated circuit 810 includes embedded on-diememory 817 such as eDRAM.

In one embodiment, the electronic system 800 also includes an externalmemory 840 that in turn may include one or more memory elements suitableto the particular application, such as a main memory 842 in the form ofRAM, one or more hard drives 844, and/or one or more drives that handleremovable media 846, such as diskettes, compact disks (CDs), digitalvariable disks (DVDs), flash memory drives, and other removable mediaknown in the art. The external memory 840 may also be embedded memory848 such as the first die in a die stack, according to an embodiment.

In accordance with one embodiment, the electronic system 800 alsoincludes a display device 850 and an audio output 860. In oneembodiment, the electronic system 800 includes an input device 870 suchas a controller that may be a keyboard, mouse, trackball, gamecontroller, microphone, voice-recognition device, or any other inputdevice that inputs information into the electronic system 800. In anembodiment, an input device 870 is a camera. In an embodiment, an inputdevice 870 is a digital sound recorder. In an embodiment, an inputdevice 870 is a camera and a digital sound recorder.

As shown herein, the integrated circuit 810 can be implemented in anumber of different embodiments, including means for implementing dierecovery in Two-Level Memory (2LM) stacked die subsystems into asemiconductor substrate package, according to any of the severaldisclosed embodiments and their equivalents, an electronic system, acomputer system, one or more methods of fabricating an integratedcircuit, and one or more methods of fabricating an electronic assemblythat includes a package substrate or a semiconductor package havingtherein means for implementing die recovery in Two-Level Memory (2LM)stacked die subsystems, according to any of the several disclosedembodiments as set forth herein in the various embodiments and theirart-recognized equivalents. The elements, materials, geometries,dimensions, and sequence of operations can all be varied to suitparticular I/O coupling requirements including array contact count,array contact configuration for a microelectronic die embedded in aprocessor mounting substrate according to any of the several disclosedpackage substrates and semiconductor packages having means forimplementing die recovery in Two-Level Memory (2LM) stacked diesubsystems and semiconductor substrate package embodiments and theirequivalents. A foundation substrate 898 may be included, as representedby the dashed line of FIG. 8. Passive devices 899 may also be included,as is also depicted in FIG. 8.

FIG. 9 illustrates an interposer 900 that includes one or more describedembodiments. The interposer 900 is an intervening substrate used tobridge a first substrate 902 to a second substrate 904. The firstsubstrate 902 may be, for instance, an integrated circuit die. Thesecond substrate 904 may be, for instance, a memory module, a computermotherboard, or another integrated circuit die. Generally, the purposeof an interposer 900 is to spread a connection to a wider pitch or toreroute a connection to a different connection. For example, aninterposer 900 may couple an integrated circuit die to a ball grid array(BGA) 906 that can subsequently be coupled to the second substrate 904.In some embodiments, the first and second substrates 902/904 areattached to opposing sides of the interposer 900. In other embodiments,the first and second substrates 902/904 are attached to the same side ofthe interposer 900. And in further embodiments, three or more substratesare interconnected by way of the interposer 900.

The interposer 900 may be formed of an epoxy resin, afiberglass-reinforced epoxy resin, a ceramic material, or a polymermaterial such as polyimide. In further implementations, the interposermay be formed of alternate rigid or flexible materials that may includethe same materials described above for use in a semiconductor substrate,such as silicon, germanium, and other group III-V and group IVmaterials.

The interposer may include metal interconnects 908 and vias 910,including but not limited to through-silicon vias (TSVs) 912. Theinterposer 900 may further include embedded devices 914, including bothpassive and active devices. Such devices include, but are not limitedto, capacitors, decoupling capacitors, resistors, inductors, fuses,diodes, transformers, sensors, and electrostatic discharge (ESD)devices. More complex devices such as radio-frequency (RF) devices,power amplifiers, power management devices, antennas, arrays, sensors,and MEMS devices may also be formed on the interposer 900. In accordancewith described embodiments, apparatuses or processes disclosed hereinmay be used in the fabrication of interposer 900.

FIG. 10 illustrates a computing device 1000 in accordance with oneimplementation of the invention. The computing device 1000 houses aboard 1002. The board 1002 may include a number of components, includingbut not limited to a processor 1004 and at least one communication chip1006. The processor 1004 is physically and electrically coupled to theboard 1002. In some implementations the at least one communication chip1006 is also physically and electrically coupled to the board 1002. Infurther implementations, the communication chip 1006 is part of theprocessor 1004.

Depending on its applications, computing device 1000 may include othercomponents that may or may not be physically and electrically coupled tothe board 1002. These other components include, but are not limited to,volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flashmemory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, atouchscreen controller, a battery, an audio codec, a video codec, apower amplifier, a global positioning system (GPS) device, a compass, anaccelerometer, a gyroscope, a speaker, a camera, and a mass storagedevice (such as hard disk drive, compact disk (CD), digital versatiledisk (DVD), and so forth).

The communication chip 1006 enables wireless communications for thetransfer of data to and from the computing device 1000. The term“wireless” and its derivatives may be used to describe circuits,devices, systems, methods, techniques, communications channels, etc.,that may communicate data through the use of modulated electromagneticradiation through a non-solid medium. The term does not imply that theassociated devices do not contain any wires, although in someembodiments they might not. The communication chip 1006 may implementany of a number of wireless standards or protocols, including but notlimited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE,GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well asany other wireless protocols that are designated as 3G, 4G, 5G, andbeyond. The computing device 1000 may include a plurality ofcommunication chips 1006. For instance, a first communication chip 1006may be dedicated to shorter range wireless communications such as Wi-Fiand Bluetooth and a second communication chip 1006 may be dedicated tolonger range wireless communications such as GPS, EDGE, GPRS, CDMA,WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing device 1000 includes an integratedcircuit die packaged within the processor 1004. In some implementationsof the invention, the integrated circuit die of the processor includesone or more devices, such as MOS-FET transistors built in accordancewith implementations of the invention. The term “processor” may refer toany device or portion of a device that processes electronic data fromregisters and/or memory to transform that electronic data into otherelectronic data that may be stored in registers and/or memory.

The communication chip 1006 also includes an integrated circuit diepackaged within the communication chip 1006. In accordance with anotherimplementation of the invention, the integrated circuit die of thecommunication chip includes one or more devices, such as MOS-FETtransistors built in accordance with implementations of the invention.

In further implementations, another component housed within thecomputing device 1000 may contain an integrated circuit die thatincludes one or more devices, such as MOS-FET transistors built inaccordance with implementations of the invention.

In various implementations, the computing device 1000 may be a laptop, anetbook, a notebook, an ultrabook, a smartphone, a tablet, a personaldigital assistant (PDA), an ultra mobile PC, a mobile phone, a desktopcomputer, a server, a printer, a scanner, a monitor, a set-top box, anentertainment control unit, a digital camera, a portable music player,or a digital video recorder. In further implementations, the computingdevice 1000 may be any other electronic device that processes data.

FIG. 11 is a flow diagram illustrating a method 1100 for implementingdie recovery in Two-Level Memory (2LM) stacked die subsystems inaccordance with described embodiments. Some of the blocks and/oroperations listed below are optional in accordance with certainembodiments. The numbering of the blocks presented is for the sake ofclarity and is not intended to prescribe an order of operations in whichthe various blocks must occur. Additionally, operations from flow 1100may be utilized in a variety of combinations.

At block 1105 the method 1100 for re-routing a memory signal path from afaulty Through Silicon Via (TSV) in a stacked semiconductor packagebegins with:

At block 1110 the method includes reading a re-routing string from TSVrepair registers of a processor functional silicon die, in which theprocessor functional silicon die forms a first layer of the stackedsemiconductor package.

At block 1115 the method includes sending the re-routing string from theprocessor functional silicon die to one or more memory dies via a secureon-board connection within the stacked semiconductor package, in whichthe one or more memory dies form a corresponding one or more memorylayers of the stacked semiconductor package.

At block 1120 the method includes programming muxes at each of aplurality of TSVs formed through the one or more memory dies with there-routing string, in which each of the plurality of TSVs traversethrough the one or more memory layers to the processor functionalsilicon die at the first layer of the stacked semiconductor package.

At block 1125 the method includes re-routing a memory signal path from adefective TSV to a redundant TSV, the redundant TSV forming a redundantphysical memory interface traversing through the memory layers to theprocessor functional silicon die at the first layer.

While the subject matter disclosed herein has been described by way ofexample and in terms of the specific embodiments, it is to be understoodthat the claimed embodiments are not limited to the explicitlyenumerated embodiments disclosed. To the contrary, the disclosure isintended to cover various modifications and similar arrangements aswould be apparent to those skilled in the art. Therefore, the scope ofthe appended claims should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements. It is tobe understood that the above description is intended to be illustrative,and not restrictive. Many other embodiments will be apparent to those ofskill in the art upon reading and understanding the above description.The scope of the disclosed subject matter is therefore to be determinedin reference to the appended claims, along with the full scope ofequivalents to which such claims are entitled.

It is therefore in accordance with the described embodiments, that:

According to one embodiment there is a stacked semiconductor package,including: a processor functional silicon die at a first layer of thestacked semiconductor package; one or more memory dies forming acorresponding one or more memory layers of the stacked semiconductorpackage; a plurality of Through Silicon Vias (TSVs) formed through theone or more memory dies, in which each of the plurality of TSVs traversethrough the one or more memory layers to the processor functionalsilicon die at the first layer of the stacked semiconductor package; aplurality of physical memory interfaces electrically interfacing the oneor more memory dies to the processor functional silicon die at the firstlayer through the memory layers via the plurality of TSVs; a redundantphysical memory interface formed by a redundant TSV traversing throughthe memory layers to the processor functional silicon die at the firstlayer through which to reroute a memory signal path from a defectivephysical memory interface at a defective TSV to a functional signal pathtraversing the redundant TSV.

According to another embodiment the stacked semiconductor package, eachTSV forms a physical memory path providing a continuous electricalinterface from one of the memory dies through the one or more memorylayers to the processor functional silicon die; and in which each memorysignal path forms a logical memory path traversing one of the physicalmemory paths through the TSVs; in which one or more of the memory signalpaths may be re-routed along the redundant physical memory interfaceusing the redundant TSV; and in which a defective physical memory pathassociated with a defective TSV may be bypassed by re-routing the memorysignal path to functional physical signal path associated with afunctional TSV or the redundant physical memory interface associatedwith the redundant TSV.

According to another embodiment the stacked semiconductor package, are-routing string computed and permanently written to the stackedsemiconductor package at a time of manufacture is used to reroute thememory signal path from the defective physical memory interface at thedefective TSV to the functional signal path traversing the redundantTSV.

According to another embodiment the stacked semiconductor package, thememory signal path re-routed from the defective physical memoryinterface to the functional signal path carries memory address and datatraffic from the memory dies between one of the memory dies and theprocessor functional silicon die.

According to another embodiment, the stacked semiconductor packagefurther includes: a package substrate layer forming a bottom layer ofthe stacked semiconductor package; and in which the processor functionalsilicon die at the first layer of the stacked semiconductor package isaffixed to the package substrate layer.

According to another embodiment the stacked semiconductor package, afirst memory die forms a first memory layer positioned atop theprocessor functional silicon die layer; and in which a second memory dieforms a second memory layer positioned atop the first memory layer.

According to another embodiment the stacked semiconductor package, thesecond memory die is electrically interfaced to the processor functionalsilicon die through the plurality of TSVs which traverse through thesecond first memory die at the first memory layer.

According to another embodiment the stacked semiconductor package, thestacked semiconductor package embodies a Two-Level-Memory (2LM) stackeddie sub-system having one or more memory silicon dies forming the one ormore memory layers and one or more functional silicon dies formed from aSystem On a Chip (SOC) functional silicon die having the processorfunctional silicon die embedded therein or a logic functional silicondie forming the processor functional silicon die or a CPU die embodyingthe processor functional silicon die at the first layer of the stackedsemiconductor package.

According to another embodiment the stacked semiconductor package, thefirst layer is formed from a System On a Chip (SOC) functional silicondie manufactured by the manufacturer of the stacked semiconductorpackage; and in which a second layer is formed from a DRAM memorysilicon die manufactured by a third party and acquired by themanufacturer of the stacked semiconductor package and integrated intothe stacked semiconductor package by the manufacturer of the stackedsemiconductor package.

According to another embodiment the stacked semiconductor package, atleast one of the memory dies are formed from a phase change memory die.

According to another embodiment the stacked semiconductor package, theprocessor functional silicon die includes a System On a Chip (SOC)functional silicon die having a secured fuse block embedded therein; andin which a re-routing string used to reroute the memory signal path fromthe defective physical memory interface to the functional signal path ispermanently written into the secured fuse block of the SOC functionalsilicon die at the time of manufacture of the stacked semiconductorpackage.

According to another embodiment the stacked semiconductor package, there-routing string is downloaded from the secured fuse block intoregisters of the SOC functional silicon die at every cold boot of thestacked semiconductor package.

According to another embodiment, there is a method for re-routing amemory signal path from a faulty Through Silicon Via (TSV) in a stackedsemiconductor package, by: reading a re-routing string from TSV repairregisters of a processor functional silicon die, in which the processorfunctional silicon die forms a first layer of the stacked semiconductorpackage; sending the re-routing string from the processor functionalsilicon die to one or more memory dies via a secure on-board connectionwithin the stacked semiconductor package, in which the one or morememory dies form a corresponding one or more memory layers of thestacked semiconductor package; programming muxes at each of a pluralityof TSVs formed through the one or more memory dies with the re-routingstring, in which each of the plurality of TSVs traverse through the oneor more memory layers to the processor functional silicon die at thefirst layer of the stacked semiconductor package; and re-routing amemory signal path from a defective TSV to a redundant TSV, theredundant TSV forming a redundant physical memory interface traversingthrough the memory layers to the processor functional silicon die at thefirst layer.

According to another embodiment of the method, the re-routing stringfrom the processor functional silicon die to the one or more memory diesvia the secure on-board connection within the stacked semiconductorpackage includes sending the re-routing string over a two wire serialinterface.

According to another embodiment of the method, the two wire interfaceincludes a clock and a serial data interface from the processorfunctional silicon die to the one or more memory dies.

According to another embodiment of the method, the two wire interfacetransmits the re-routing string via a serial data one bit at a time,with one bit transmitted per clock cycle.

According to another embodiment, the method further includes: storingthe re-routing string within a detour registers at each of the one ormore memory dies; and in which programming the muxes at each of aplurality of TSVs with the re-routing string includes programming themuxes at each of the plurality of TSVs at each of the one or more memorydies from the detour registers at each of the one or more memory dieshaving the re-routing string stored therein.

According to another embodiment of the method, the secure on-boardconnection includes a side band interface the stacked semiconductorpackage which is inaccessible external to the stacked semiconductorpackage such that any data flow transferred through the secure onboardconnection cannot be derived from outside of the stacked semiconductorpackage.

According to another embodiment of the method, the TSVs form TSV micropillars oriented vertically through the entire stack of the one or morememory dies, electrically interfacing the processor functional silicondie with the one or more memory dies of the stacked semiconductorpackage.

According to another embodiment of the method, the processor functionalsilicon die includes a System On a Chip (SOC) functional silicon diehaving a secured fuse block embedded therein; and in which there-routing string used for re-routing the memory signal path from thedefective TSV to the redundant TSV is permanently written into thesecured fuse block of the SOC functional silicon die at the time ofmanufacture of the stacked semiconductor package.

According to another embodiment, the method further includes:downloading the re-routing string from the secured fuse block intoregisters of the SOC functional silicon die at every cold boot of thestacked semiconductor package; and shifting the re-routing string fromthe registers of the SOC functional silicon die to detour registers atthe one or more memory dies via a secure on-board connection of thestacked semiconductor package as part of the cold boot process for thestacked semiconductor package.

According to another embodiment of the method, the stacked semiconductorpackage embodies a Two-Level-Memory (2LM) stacked die sub-system havingone or more memory silicon dies forming the one or more memory layersand one or more functional silicon dies formed from a System On a Chip(SOC) functional silicon die having the processor functional silicon dieembedded therein or a logic functional silicon die forming the processorfunctional silicon die or a CPU die embodying the processor functionalsilicon die at the first layer of the stacked semiconductor package.

According to yet another embodiment there is an electronics moduleincluding: a printed circuit board; a stacked semiconductor packageelectrically interfaced to the printed circuit board; and in which thestacked semiconductor package includes: (i) a substrate layer; (ii) aprocessor functional silicon die at a first layer of the stackedsemiconductor package atop the substrate layer; (iii) one or more memorydies forming a corresponding one or more memory layers of the stackedsemiconductor package; (iv) a plurality of Through Silicon Vias (TSVs)formed through the one or more memory dies, in which each of theplurality of TSVs traverse through the one or more memory layers to theprocessor functional silicon die at the first layer of the stackedsemiconductor package; (v) a plurality of physical memory interfaceselectrically interfacing the one or more memory dies to the processorfunctional silicon die at the first layer through the memory layers viathe plurality of TSVs; (vi) a redundant physical memory interface formedby a redundant TSV traversing through the memory layers to the processorfunctional silicon die at the first layer through which to reroute amemory signal path from a defective physical memory interface at adefective TSV to a functional signal path traversing the redundant TSV.

According to another embodiment of the electronics module, theelectronics module includes one of: a drone and robot controlelectronics module; a smartphone electronics module; a tabletelectronics module; a gesture control electronics module for a computer;a 3D photography electronics module; a 3D immersive gaming electronicsmodule; a face recognition electronics module to perform facerecognition base security in lieu of alphanumerical passwords; an imagecapture device electronics module having one or more optical andComplementary metal-oxide-semiconductor (CMOS) components affixed to theprinted circuit board as the top side or bottom side components; a depthsensing camera electronics module to perform any of stereoscopic imagingdepth sensing, coded light depth sensing, or laser time of flight depthsensing.

According to another embodiment of the electronics module, theelectronics module includes is embedded within a wearable technology tobe worn as one of: a clothing item; sports attire; a shoe; fashionelectronics to be worn as a clothing item or an accessory; tech togs tobe worn as a clothing item or an accessory; or fashionable technology tobe worn as a clothing item or an accessory.

What is claimed is:
 1. A stacked semiconductor package, comprising: aprocessor functional silicon die at a first layer of the stackedsemiconductor package; one or more memory dies forming a correspondingone or more memory layers of the stacked semiconductor package; aplurality of Through Silicon Vias (TSVs) formed through the one or morememory dies, wherein each of the plurality of TSVs traverse through theone or more memory layers to the processor functional silicon die at thefirst layer of the stacked semiconductor package; a plurality ofphysical memory interfaces electrically interfacing the one or morememory dies to the processor functional silicon die at the first layerthrough the memory layers via the plurality of TSVs; a redundantphysical memory interface formed by a redundant TSV traversing throughthe memory layers to the processor functional silicon die at the firstlayer through which to reroute a memory signal path from a defectivephysical memory interface at a defective TSV to a functional signal pathtraversing the redundant TSV.
 2. The stacked semiconductor package ofclaim 1: wherein each TSV forms a physical memory path providing acontinuous electrical interface from one of the memory dies through theone or more memory layers to the processor functional silicon die; andwherein each memory signal path forms a logical memory path traversingone of the physical memory paths through the TSVs; wherein one or moreof the memory signal paths may be re-routed along the redundant physicalmemory interface using the redundant TSV; and wherein a defectivephysical memory path associated with a defective TSV may be bypassed byre-routing the memory signal path to functional physical signal pathassociated with a functional TSV or the redundant physical memoryinterface associated with the redundant TSV.
 3. The stackedsemiconductor package of claim 1: wherein a re-routing string computedand permanently written to the stacked semiconductor package at a timeof manufacture is used to reroute the memory signal path from thedefective physical memory interface at the defective TSV to thefunctional signal path traversing the redundant TSV.
 4. The stackedsemiconductor package of claim 1: wherein the memory signal pathre-routed from the defective physical memory interface to the functionalsignal path carries memory address and data traffic from the memory diesbetween one of the memory dies and the processor functional silicon die.5. The stacked semiconductor package of claim 1, further comprising: apackage substrate layer forming a bottom layer of the stackedsemiconductor package; and wherein the processor functional silicon dieat the first layer of the stacked semiconductor package is affixed tothe package substrate layer.
 6. The stacked semiconductor package ofclaim 5: wherein a first memory die forms a first memory layerpositioned atop the processor functional silicon die layer; and whereina second memory die forms a second memory layer positioned atop thefirst memory layer.
 7. The stacked semiconductor package of claim 6:wherein the second memory die is electrically interfaced to theprocessor functional silicon die through the plurality of TSVs whichtraverse through the second first memory die at the first memory layer.8. The stacked semiconductor package of claim 1, wherein the stackedsemiconductor package embodies a Two-Level-Memory (2LM) stacked diesub-system having one or more memory silicon dies forming the one ormore memory layers and one or more functional silicon dies formed from aSystem On a Chip (SOC) functional silicon die having the processorfunctional silicon die embedded therein or a logic functional silicondie forming the processor functional silicon die or a CPU die embodyingthe processor functional silicon die at the first layer of the stackedsemiconductor package.
 9. The stacked semiconductor package of claim 1:wherein the first layer is formed from a System On a Chip (SOC)functional silicon die manufactured by the manufacturer of the stackedsemiconductor package; and wherein a second layer is formed from a DRAMmemory silicon die manufactured by a third party and acquired by themanufacturer of the stacked semiconductor package and integrated intothe stacked semiconductor package by the manufacturer of the stackedsemiconductor package.
 10. The stacked semiconductor package of claim 1,wherein at least one of the memory dies are formed from a phase changememory die.
 11. The stacked semiconductor package of claim 1: whereinthe processor functional silicon die comprises a System On a Chip (SOC)functional silicon die having a secured fuse block embedded therein; andwherein a re-routing string used to reroute the memory signal path fromthe defective physical memory interface to the functional signal path ispermanently written into the secured fuse block of the SOC functionalsilicon die at the time of manufacture of the stacked semiconductorpackage.
 12. The stacked semiconductor package of claim 11: wherein there-routing string is downloaded from the secured fuse block intoregisters of the SOC functional silicon die at every cold boot of thestacked semiconductor package.
 13. A method for re-routing a memorysignal path from a faulty Through Silicon Via (TSV) in a stackedsemiconductor package, wherein the method comprises: reading are-routing string from TSV repair registers of a processor functionalsilicon die, wherein the processor functional silicon die forms a firstlayer of the stacked semiconductor package; sending the re-routingstring from the processor functional silicon die to one or more memorydies via a secure on-board connection within the stacked semiconductorpackage, wherein the one or more memory dies form a corresponding one ormore memory layers of the stacked semiconductor package; programmingmuxes at each of a plurality of TSVs formed through the one or morememory dies with the re-routing string, wherein each of the plurality ofTSVs traverse through the one or more memory layers to the processorfunctional silicon die at the first layer of the stacked semiconductorpackage; and re-routing a memory signal path from a defective TSV to aredundant TSV, the redundant TSV forming a redundant physical memoryinterface traversing through the memory layers to the processorfunctional silicon die at the first layer.
 14. The method of claim 13,wherein sending the re-routing string from the processor functionalsilicon die to the one or more memory dies via the secure on-boardconnection within the stacked semiconductor package comprises sendingthe re-routing string over a two wire serial interface.
 15. The methodof claim 14, wherein the two wire interface comprises a clock and aserial data interface from the processor functional silicon die to theone or more memory dies.
 16. The method of claim 14, wherein the twowire interface transmits the re-routing string via a serial data one bitat a time, with one bit transmitted per clock cycle.
 17. The method ofclaim 13, further comprising: storing the re-routing string within adetour registers at each of the one or more memory dies; and whereinprogramming the muxes at each of a plurality of TSVs with the re-routingstring comprises programming the muxes at each of the plurality of TSVsat each of the one or more memory dies from the detour registers at eachof the one or more memory dies having the re-routing string storedtherein.
 18. The method of claim 13, wherein the secure on-boardconnection comprises a side band interface the stacked semiconductorpackage which is inaccessible external to the stacked semiconductorpackage such that any data flow transferred through the secure onboardconnection cannot be derived from outside of the stacked semiconductorpackage.
 19. The method of claim 13, wherein the TSVs form TSV micropillars oriented vertically through the entire stack of the one or morememory dies, electrically interfacing the processor functional silicondie with the one or more memory dies of the stacked semiconductorpackage.
 20. The method of claim 13: wherein the processor functionalsilicon die comprises a System On a Chip (SOC) functional silicon diehaving a secured fuse block embedded therein; and wherein the re-routingstring used for re-routing the memory signal path from the defective TSVto the redundant TSV is permanently written into the secured fuse blockof the SOC functional silicon die at the time of manufacture of thestacked semiconductor package.
 21. The method of claim 20, furthercomprising: downloading the re-routing string from the secured fuseblock into registers of the SOC functional silicon die at every coldboot of the stacked semiconductor package; and shifting the re-routingstring from the registers of the SOC functional silicon die to detourregisters at the one or more memory dies via a secure on-boardconnection of the stacked semiconductor package as part of the cold bootprocess for the stacked semiconductor package.
 22. The method of claim13, wherein the stacked semiconductor package embodies aTwo-Level-Memory (2LM) stacked die sub-system having one or more memorysilicon dies forming the one or more memory layers and one or morefunctional silicon dies formed from a System On a Chip (SOC) functionalsilicon die having the processor functional silicon die embedded thereinor a logic functional silicon die forming the processor functionalsilicon die or a CPU die embodying the processor functional silicon dieat the first layer of the stacked semiconductor package.
 23. Anelectronics module comprising: a printed circuit board; a stackedsemiconductor package electrically interfaced to the printed circuitboard; and wherein the stacked semiconductor package comprises: (i) asubstrate layer; (ii) a processor functional silicon die at a firstlayer of the stacked semiconductor package atop the substrate layer;(iii) one or more memory dies forming a corresponding one or more memorylayers of the stacked semiconductor package; (iv) a plurality of ThroughSilicon Vias (TSVs) formed through the one or more memory dies, whereineach of the plurality of TSVs traverse through the one or more memorylayers to the processor functional silicon die at the first layer of thestacked semiconductor package; (v) a plurality of physical memoryinterfaces electrically interfacing the one or more memory dies to theprocessor functional silicon die at the first layer through the memorylayers via the plurality of TSVs; (vi) a redundant physical memoryinterface formed by a redundant TSV traversing through the memory layersto the processor functional silicon die at the first layer through whichto reroute a memory signal path from a defective physical memoryinterface at a defective TSV to a functional signal path traversing theredundant TSV.
 24. The electronics module of claim 23, wherein theelectronics module comprises one of: a drone and robot controlelectronics module; a smartphone electronics module; a tabletelectronics module; a gesture control electronics module for a computer;a 3D photography electronics module; a 3D immersive gaming electronicsmodule; a face recognition electronics module to perform facerecognition base security in-lieu of alphanumerical passwords; an imagecapture device electronics module having one or more optical andComplementary metal-oxide-semiconductor (CMOS) components affixed to theprinted circuit board as the top side or bottom side components; a depthsensing camera electronics module to perform any of stereoscopic imagingdepth sensing, coded light depth sensing, or laser time of flight depthsensing.
 25. The electronics module of claim 23, wherein the electronicsmodule comprises is embedded within a wearable technology to be worn asone of: a clothing item; sports attire; a shoe; fashion electronics tobe worn as a clothing item or an accessory; tech togs to be worn as aclothing item or an accessory; or fashionable technology to be worn as aclothing item or an accessory.